The present invention relates generally to bus priority allocation in a digital system and more particularly to a method of allocating access in a bus arrangement among a plurality of discrete and/or integrated modules and an associated apparatus.
Many schemes have been implemented for purposes of providing prioritized access to bus arrangements in digital systems. One of skill in the art will readily recognize that the concept of priority in a digital system is crucial since certain components or modules such as, for example, a CPU require low latency accesses to the bus arrangement. At the same time, however, other groups of components or modules may require access to the bus arrangement in a way which provides for reasonably low latency access and for fairness among the groups, particularly in instances where the various components or modules which make up these groups are in substantially continuous contention for the use of the bus arrangement. It is submitted that bus contention between module/component groups has become a significant problem in view of the recent and continuing movement toward streaming type processing environments since bus arrangements experience higher utilization levels, as will be further discussed at an appropriate point below.
In prior art systems, groups of modules or components which require substantially equal bus access are pre-assigned the same (hereinafter multi-assigned) priority level. Thereafter, during the operation of such a system, some sort of mechanism is employed each time a multi-assigned priority level is to receive a bus grant so as to delegate the grant to one of that level's multi-assigned modules in an attempt to ensure fair bus access. For example, a random number generator may be utilized in determining which module actually receives the bus grant. Unfortunately, the aforedescribed scheme adds considerable complexity through the need for the mechanism which is required to select one module from a group of multi-assigned modules which are on a particular priority level.
Another concern with regard to past priority allocation implementations relates to flexibility. Specifically, typical priority allocation implementations do not provide for adjusting relative priorities of components/modules during the operation of the system. That is, once an initial priority configuration has been established at system startup, that startup configuration is maintained for the duration of system operation. This inflexibility may be disadvantageous in a variety of different circumstances as the operation of a system progresses. For example, processing may move from a first task using one group of modules to a second task using another group of modules. If system priorities do not adjust accordingly, the overall throughput of the system may suffer.
As mentioned briefly above, still another concern resides in the problem of bus contention with regard to the way in which priority allocation implementations of the past operate in a streaming environment. Specifically, it should be appreciated that different modules interconnected by one bus arrangement may possess different data transfer capabilities. In many instances, these differences in transfer rate capabilities are handled by using a buffer to store data at a rate which is determined by a source module. Thereafter, the data is transferred to a destination module over the bus arrangement at a rate which is determined by the destination module. Buffering, however, is disadvantageous for several different reasons. As a first reason, relatively expensive local memory is required at one of the modules to perform the buffering task whereby to increase overall costs. As a second reason, this buffering approach is inherently inconsistent with an efficient streaming environment as is contemplated by the present invention.
As will be seen hereinafter, the present invention provides a highly advantageous priority allocation approach and associated apparatus which resolve the foregoing concerns and which provides still further advantages that have not been seen heretofore.